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Acta scientiarum naturalium Universitatis Pekinensis

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Analysis and Design of Low Power XOR-XNOR Circuits

LAN Jinghong, WANG Fang, JI Lijiu, JIA Song   

  1. Department of Microelectronics, Peking University, Beijing, 100871
  • Received:2005-06-27 Online:2006-05-20 Published:2006-05-20

Abstract: Two novel low power pass transistor based XOR-XNOR circuits are proposed, UPPL (Unsymmetrical Push Pull Pass Transistor Logic) and CPPL (Complementary Push Pull Pass Transistor Logic). They both input single rail signals and output dual rail signals, which can get XOR and XNOR signals simultaneously. The output signals are full swing voltage. Hspice simulation under 0.18μm technology 1.8V voltage showed improvement on speed and power-delay product compared with some other circuits. Compared with the latest circuits, which was proposed by Mohamed Elgamel in 2003, the UPPL and CPPL circuits have 61.0% and 58.4% decreases on power delay product respectively without load. And with fanout three, they have 25.3% and 45.3% decreases respectively.