Acta scientiarum naturalium Universitatis Pekinensis
HUANG Shuilong1, WANG Zhihua
A programmable dual modulus divider is proposed. The circuit mainly includes three building blocks: prescaler, 8-bit programmable counter and ΣΔ modulator. Two operation modes (integer/fractional-N) are achieved by switching on/off the output signal of the ΣΔ modulator. Only a programmable counter is needed for the swallow pulse divider. The prescaler was designed by using the improved dynamic TSPC triggers, and the other blocks were realized by the way of digital synthesis, placing and routing. Based on 0.18μm 1.8V CMOS technology, SpectreVerilog simulations verify that it can operate within the division ratio of 56-2 047 with 2GHz maximum operation frequency and <4mA current dissipation. The circuit is very simple and can be used in the high performance PLL frequency synthesizer.
HUANG Shuilong,WANG Zhihua. A Generic Programmable Dual Modulus Divider[J].Acta scientiarum naturalium Universitatis Pekinensis, 2007, 43(1): 109-112.
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