Acta scientiarum naturalium Universitatis Pekinensis
SUN Zhao1, WANG Yong
Verification is very important in designing digital systems. It has become a bottleneck in the modern digital system design cycle. In an effort to improve current verification method based on simulation, this paper presents a method for the generation of simulation vectors using FSM. It can improve the coverage of the state space.
SUN Zhao,WANG Yong. A High Efficient Method to Generate the Verification Vector of ICs[J].Acta scientiarum naturalium Universitatis Pekinensis, 2007, 43(1): 92-95.
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