ISSN 1002-1027  CN 11-2952/G2

Acta scientiarum naturalium Universitatis Pekinensis

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A High Efficient Method to Generate the Verification Vector of ICs

SUN Zhao1, WANG Yong   

  • Received:2006-03-06 Online:2007-01-20 Published:2007-01-20

Abstract: Verification is very important in designing digital systems. It has become a bottleneck in the modern digital system design cycle. In an effort to improve current verification method based on simulation, this paper presents a method for the generation of simulation vectors using FSM. It can improve the coverage of the state space.